基于UCC28730的具有 PSR 和唤醒监控功能的恒压、恒流控制器

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基于UCC28730的具有 PSR 和唤醒监控功能的恒压、恒流控制器

　　1 特性

　　支持零功耗 (<5mW) 待机

　　具有智能唤醒检测功能，可采用最小输出电容

　　一次侧稳压 (PSR) 功能免除了对光耦合器的需求

　　线路和负载具有 ±5% 电压调节和电流调节能力

　　700V 启动开关

　　最大开关频率 83kHz 支持低待机功耗充电器设计

　　针对最高总体效率的谐振环谷值开关运行

　　具有频率抖动特性，确保符合 EMI 标准

　　针对金属氧化物半导体场效应晶体管 (MOSFET) 的已钳制栅极驱动输出

　　过压、欠压和过流保护功能

　　可编程电缆补偿

　　小外形尺寸集成电路 (SOIC)-7 封装

　　2 应用

　　智能手机、平板电脑以及其他消费类电子产品适配器和充电器

　　TV 和监视器电源

　　家用电器和工业自动化 SMPS

备用和辅助电源

TI产品现货库存在线购买：https://www.iczoom.com/brand/509-c-1-20.html

　　3 说明

　　UCC28730 隔离式反激电源控制器无需使用光耦合器即可提供恒定电压 (CV) 和恒定电流 (CC) 输出稳压，并且具有唤醒信号检测功能，可改善大型负载阶跃瞬态响应。 最小开关频率 30Hz 可促进实现低于 5mW 的无负载功耗。 此器件处理来自一次侧电源开关和辅助反激式绕组的信息，以对输出电压和电流进行精确控制。 唤醒监视功能可与 UCC24650 这类二次侧报警器件搭配使用，只需最小输出电容即可快速响应大型负载阶跃。

　　内部采用 700V 启动开关，可动态控制工作状态并定制调制配置文件，支持超低待机功耗，并且不会影响启动时间或输出瞬态响应。 UCC28730 中的控制算法使得运行效率符合甚至超过现行标准。 带有谷值开关的断续传导模式 (DCM) 降低了开关损耗。 调制开关频率和一次侧峰值电流振幅(FM 和 AM)可在整个负载和线路范围内保持高转换效率。

　　4.1.1 VDD (Device Bias Voltage Supply)

　　The VDD pin connects to a by-pass capacitor to ground. The turn-on UVLO threshold is 21 V and turn-off UVLO threshold is 7.7 V with an available operating range up to 35 V on VDD. The typical USB charging specification requires the output current to operate in Constant-Current mode from 5 V down to at least 2 V, which is easily achieved with a nominal VVDD of approximately 20 V. The additional VDD headroom up to 35 V allows for VVDD to rise due to the leakage energy delivered to the VDD capacitor during high-load conditions.

　　4.1.2 GND (Ground)

　　UCC28730 has a single ground reference external to the device for the gate-drive current and analog signal reference. Place the VDD-bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and CS signal pins.

　　4.1.3 HV (High Voltage Startup)

　　The HV pin connects directly to the bulk capacitor to provide startup current to the VDD capacitor. The typical startup current is approximately 250 µA which provides fast charging of the VDD capacitor. The internal HV startup device is active until VVDD exceeds the turn-on UVLO threshold of 21 V at which time the HV startup device turns off. In the off state the HV leakage current is very low to minimize stand-by losses of the controller. When VVDD falls below the 7.7-V UVLO turn-off threshold the HV startup device turns on.

　　4.1.4 DRV (Gate Drive)

　　The DRV pin connects to the MOSFET gate pin, usually through a series resistor. The gate driver provides a gate-drive signal limited to 14 V. The turn-on characteristic of the driver is a 29-mA current source which limits the turn-on dv/dt of the MOSFET drain and reduces the leading-edge current spike, while still providing a gate-drive current to overcome the Miller plateau. The gate-drive turn-off current is determined by the RDS(on) of the low-side driver and any external gate drive resistance. Adding external gate resistance reduces the MOSFET drain turn-off dv/dt, if necessary. Such resistance value is generally higher than the typical 10 Ω commonly used to damp resonance. However, calculation of the external resistance value to achieve a specific dv/dt involves MOSFET parameters beyond the scope of this datasheet.

　　4.1.5 CBC (Cable Compensation)

　　The cable compensation pin is connected to a resistor to ground to program the amount of output voltage compensation needed to offset cable resistance. The cable compensation circuit generates a 0 to 3.13-V voltage level on the CBC pin corresponding to 0 A to IOCC maximum output current. The resistance selected on the CBC pin programs a current mirror that is summed into the VS feedback divider therefore increasing the regulation voltage as IOUT increases. There is an internal series resistance of 28 kΩ to the CBC pin which sets a maximum cable compensation for a 5-V output to approximately 400 mV when CBC is shorted to ground.

　　The UCC28730 is an isolated-flyback power supply controller which provides accurate voltage and constant current regulation using primary-side winding sensing, eliminating the need for opto-coupler feedback circuits. The controller operates in discontinuous conduction mode with valley switching to minimize switching losses. The modulation scheme is a combination of frequency modulation and primary peak-current modulation to provide high conversion efficiency across the load range. The control law provides a wide dynamic operating range of output power which facilitates the achievement of <5-mW stand-by power.

　　During low-power operating levels the device has power management features to reduce the device operating current at switching frequencies less than 28 kHz. The UCC28730 includes features in the pulse-width modulator to reduce the EMI peak energy at the fundamental switching frequency and its harmonics. Accurate voltage and current regulation, fast dynamic response, and fault protection are achieved with primary-side control. A complete charger solution can be realized with a straightforward design process, low cost, and low component-count.