基于UCC24650的Output Voltage Monitor with Wake-Up Alarm Signaling

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　　1 特性

　　具有出色的负载瞬态性能和零待机功耗

　　实现最小输出电容，以降低 ΔVOUT

　　无需外部元件

　　<50μA 的器件电流补偿(典型值)

　　5V 至 28V 输出监视能力

　　3% 电压浮动检测(专利申请中)

　　200V 唤醒开关

　　可使能和禁用 SR 控制器、继电器控制或其他辅助电路

　　5 引脚小外形尺寸晶体管 (SOT)-23 封装

　　2 应用

　　< 5mW 零功耗待机应用

　　面向消费类电子产品的适配器和充电器

　　智能手机、平板电脑、机顶盒

　　TV 和监视器电源

　　家用电器开关电源 (SMPS)

　　冰箱、洗衣机、空调

　　面向照明和家用自动化的工业电源

　　3 说明

　　UCC24650 是一款易于使用的二次侧电压监视器，可定期测量其自身的 VDD 电压。 当相对上一读数存在 3% 浮动时，会向接收一次侧稳压 (PSR) 控制器发送唤醒警报信号。 该器件功耗较低，有助于在许多应用中实现小于 5mW 的零功耗待机损耗。

　　接地基准整流器上连接了一个内部 200V 金属氧化物半导体场效应晶体管 (MOSFET) 开关，可向反激变压器二次侧绕组提供限流脉冲，从而将信号耦合至一次侧控制器。 在检测到控制器驱动的开关活动之前，将以 33kHz 的频率重复发送该信号。

　　相对浮动检测功能可将电压调节至 5V 与 28V 之间的任一电压。唤醒警报功能可实现超低待机频率，从而以最大限度降低开关损耗，并减小响应重载阶跃所需的输出电容。 此监视器与能够检测唤醒信号的控制器搭配使用，例如 UCC28730 PSR 反激控制器。

　　UCC24650 还提供了使能和禁用信号，可用于在无载条件下控制二次侧电路，从而降低待机功耗。 此类电路可以是同步整流控制器或继电器驱动器等。

　　The UCC24650 is a voltage monitor designed to alert a companion primary-side controller device when the monitor detects a relative droop of approximately 3% on its VDD input. Commonly known as a wake-up device, the UCC24650 is normally used in isolated-flyback power supply applications using primary-side regulation (PSR). Because the PSR controller may operate at very-low frequencies during light-load or no-load conditions, it cannot detect a sudden load step that may occur between power cycles and the output voltage may fall out of regulation. The UCC24650 can detect the voltage droop and wake-up a compatible PSR controller to increase its switching frequency before the output falls too low. This action significantly reduces the amount of output capacitance needed to achieve an acceptable transient response.

　　At the end of each power cycle delivered by the PSR controller, the UCC24650 droop monitor refreshes an internally stored voltage scaled to 97% of the VDD voltage. If the monitor detects a droop of VDD to the level of the stored voltage, the WAKE signal is connected to GND by an internal low-impedance switch. The WAKE signal transmits a current pulse across the isolation transformer to a compatible PSR controller, such as the UCC28730, capable of detecting the wake-up signal on the primary side of the transformer.

　　The UCC24650 is also capable of disabling a compatible SR controller, such as the UCC24610, during light-load conditions to minimize standby power. The ENS output signal is driven low after a fixed sustained count of low-frequency power pulses, and can re-enable the SR controller after a cumulative count of 32 higher-frequency power pulses. The ENS output may also be used to drive other secondary circuitry compatible with the ENS operating parameters.

　　The UCC24650 device can operate over a bias supply voltage range from approximately 4 to 28 V. All functions are disabled and bias supply current is quiescent until the UVLO turn-on threshold is exceeded. When enabled, all functions remain operational until the VDD voltage falls below the UVLO turn-off threshold.

　　To ensure that wake-up pulses can be successfully driven, make sure the output voltage droop at VDD during a load-step does not fall below the maximum UVLO turn-off threshold before at least one wake-up pulse can be issued. This imposes a practical limit on the lowest nominal no-load voltage allowable at VDD before the maximum load step is applied.

　　After the UCC24650 has been turned on and enabled, the WAKE pin is used to detect the power-cycle waveforms at the flyback transformer secondary winding. This winding voltage can be at wide-ranging levels, but the PCD block arms the sample-and-hold (S&H) block to acquire a reference voltage reading at VDD when certain criteria are met. The PCD block triggers the S&H block at the end of the demagnetization time, tDM, provided that the voltage at WAKE has remained below the VPCD threshold for longer than tPCD(min), to ensure that the sampled voltage is free of transient deviations and noise. Consequently, this imposes a minimum demagnetization-time constraint on the flyback design to provide adequate signal for the PCD function.

　　Figure 11 illustrates the behavior of the device for power-cycles that do meet the criteria and for those that do not. The wake-up reference voltage, which is stored internally as approximately 97% of the sampled VDD voltage, is updated at every PCD pulse to change proportionally with the changes in output voltage. Disturbances at the WAKE input which do not meet the PCD criteria do not affect the stored reference voltage.

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