基于UCC28740的具有光电耦合器反馈的恒压、恒流反激控制器

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基于UCC28740的具有光电耦合器反馈的恒压、恒流反激控制器

　　1 特性

　　低于 10mW 的空载功耗能力

　　具有针对恒定电压 (CV) 的光耦合反馈和针对恒定电流 (CC) 的初级侧调节 (PSR)

　　在线路和负载上实现 ±1% 电压调节和 ±5% 电流调节

　　700V 启动开关

　　100kHz 最大开关频率可实现高功率密度充电器设计

　　针对最高总体效率的谐振环谷值开关运行

　　简化电磁干扰 (EMI) 兼容性的频率抖动

　　针对金属氧化物半导体场效应晶体管 (MOSFET) 的已钳制栅极驱动输出

　　过压、低线路和过流保护功能

　　小外形尺寸集成电路 (SOIC)-7 封装

　　2 应用

　　用于消费类电子产品的 USB 兼容适配器和充电器

　　智能手机

　　平板电脑

　　摄像机

　　电视和台式机的待机电源

白色家电

TI产品现货库存在线购买：https://www.iczoom.com/brand/509-c-1-20.html

　　3 说明

　　UCC28740 隔离式反激电源控制器使用光耦合器来提供恒定电压 (CV)，从而改善对大型负载阶跃的瞬态响应。恒流 (CC) 调节通过一次侧稳压 (PSR) 技术来实现。此器件处理光耦合反馈信息和来自辅助反激式绕组的信息，以实现对输出电压和电流的精准高性能控制。

　　内部采用 700V 启动开关，可动态控制工作状态并定制调制配置文件，支持超低待机功耗，并且不会影响启动时间或输出瞬态响应。

　　UCC28740 中的控制算法使得运行效率满足或者超过适用标准。驱动输出接至一个 MOSFET 电源开关。带有谷值开关的断续传导模式 (DCM) 减少了开关损耗。开关频率的调制和初级电流峰值振幅(FM 和 AM)在整个负载和线路范围内保持较高的转换效率。

　　此控制器有一个 100kHz 的最大开关频率并且一直保持对变压器内峰值初级电流的控制。保护 特性 有助于抑制一次侧和二次侧应力分量。170Hz 的最小开关频率可轻松实现低于 10mW 的无负载功耗。

　　The UCC28740 is a flyback power-supply controller which provides high-performance voltage regulation using an optically coupled feedback signal from a secondary-side voltage regulator. The device provides accurate constant-current regulation using primary-side feedback. The controller operates in discontinuous-conduction mode (DCM) with valley-switching to minimize switching losses. The control law scheme combines frequency with primary peak-current amplitude modulation to provide high conversion efficiency across the load range. The control law provides a wide dynamic operating range of output power which allows the power-supply designer to easily achieve less than 30-mW standby power dissipation using a standard shunt-regulator and optocoupler. For a target of less than 10-mW standby power, careful loss-management design with a low-power regulator and high-CTR optocoupler is required.

　　During low-power operating conditions, the power-management features of the controller reduce the device-operating current at switching frequencies below 32 kHz. At and above this frequency, the UCC28740 includes features in the modulator to reduce the EMI peak energy of the fundamental switching frequency and harmonics. A complete low-cost and low component-count charger-solution is realized using a straight-forward design process.

　　7.3.2 Valley-Switching and Valley-Skipping

　　The UCC28740 uses valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI, and to minimize the turnon current spike at the current-sense resistor. The controller operates in valley-switching in all load conditions unless the VDS ringing diminishes to the point where valleys are no longer detectable.

　　As shown in Figure 11, the UCC28740 operates in a valley-skipping mode (also known as valley-hopping) in most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest available VDS voltage.

　　Figure 11. Valley-Skipping Mode

　　Valley-skipping modulates each switching cycle into discrete period durations. During FM operation, the switching cycles are periods when energy is delivered to the output in fixed packets, where the power-per-cycle varies discretely with the switching period. During operating conditions when the switching period is relatively short, such as at high-load and low-line, the average power delivered per cycle varies significantly based on the number of valleys skipped between cycles. As a consequence, valley-skipping adds additional ripple voltage to the output with a frequency and amplitude dependent upon the loop-response of the shunt-regulator. For a load with an average power level between that of cycles with fewer valleys skipped and cycles with more valleys skipped, the voltage-control loop modulates the FB current according to the loop-bandwidth and toggles between longer and shorter switching periods to match the required average output power.

　　7.3.3 Startup Operation

　　An internal high-voltage startup switch, connected to the bulk-capacitor voltage (VBULK) through the HV pin, charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 µA to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turnon threshold the controller is enabled, the converter starts switching, and the startup switch turns off.

　　Often at initial turnon, the output capacitor is in a fully discharged state. The first three switching-cycle current peaks are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these three cycles, if the sampled voltage at VS is less than 1.33 V, the controller operates in a special startup mode. In this mode, the primary current peak amplitude of each switching cycle is limited to approximately 0.63 × IPP(max) and DMAGCC increases from 0.425 to 0.735. These modifications to IPP(max) and DMAGCC during startup allows high-frequency charge-up of the output capacitor to avoid audible noise while the demagnetization voltage is low. Once the sampled VS voltage exceeds 1.38 V, DMAGCC is restored to 0.425 and the primary current peak resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to maintain a constant output current until the output voltage enters regulation. Thereafter, the controller responds to the condition dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor charges to 21 V plus the time the output capacitor charges.