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基于TPS717 的线性稳压器

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发表于 2018-11-7 17:31:20 | 显示全部楼层 |阅读模式
  1 特性
  输入电压:+2.5V +6.5V
  提供多个输出版本:
  固定输出电压范围:0.9V 5V
  可调节输出电压范围为 0.9V 6.2V
  超高 PSRR
  1kHz 70dB100kHz 67dB1MHz 45dB
  出色的负载和线路瞬态响应
  超低压降:150mA 时为 170mV(典型值)
  低噪声:30μVRMS 典型值(100Hz 100kHz)
  小型 5 引脚 SC-702mm × 2mm 晶圆级小外形无引线 (WSON)-6 封装和 1.5mm × 1.5mm WSON-6 封装
  2 应用
  摄像机传感器电源
  移动电话耳机
  掌上电脑 (PDA) 和智能手机
  无线 LANBluetooth®
  3 说明
  TPS717xx 系列低压降 (LDO)、低功耗线性稳压器采用超小型 5 引脚小外形尺寸晶体管 (SOT) 封装,其具有非常高的电源抑制比 (PSRR),同时能够保持 45μA 的超低接地电流。 该系列稳压器采用先进的双极 CMOS (BiCMOS) 工艺和功率金属氧化物半导体场效应晶体管 (PMOSFET) 无源器件,可实现快速启动、超低噪声、优异的瞬态响应以及出色的 PSRR 性能。 TPS717xx 器件与 1μF 陶瓷输出电容一起工作时可保持稳定,并且使用了一个精确的电压基准和反馈环路,以在所有负载、线路、过程和温度变化范围内实现至少 3% 的精度。 该器件系列的额定温度范围为 TJ = -40°C 125°C,并且提供小型 SOT (SC70-5) 封装、带有散热焊盘的
  2mm× 2mm WSON-6 封装以及 1.5mm x 1.5mm WSON-6 封装,非常适合小尺寸便携式设备(例如无线手持设备和 PDA)
  4Detailed Description
  4.1 Overview
  The TPS717xx family of low-dropout (LDO) regulators combines the high performance required by many RF and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain, high-bandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also make the TPS717xx family of devices an excellent choice for battery-powered applications. All versions have thermal and overcurrent protection.
  4.2 Functional Block Diagrams
  Figure 31. Fixed Voltage Versions
  Figure 32. Adjustable Voltage Version
  4.3 Feature Description
  4.3.1 Internal Current Limit
  The TPS717xx internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do not operate the device in a current-limit state for extended periods of time.
  The PMOS pass element in the TPS717xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.
  4.3.2 Shutdown
  The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.
  4.3.3 Startup and Noise Reduction Capacitor
  Fixed voltage versions of the TPS717xx use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration.
  Note that for fastest startup, apply VIN first, then the enable pin (EN) driven high. If EN is tied to IN, startup is somewhat slower. Refer to Figure 29 in Typical Characteristics. The quick-start switch is closed for approximately 135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller capacitor.
  For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize output regulation performance for lower output voltages. This configuration results in an additional resistor in the quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output voltages below 1.6 V.
  Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V:
  Equation 1.
  4.3.4 Undervoltage Lockout (UVLO)
  The TPS717xx uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored on the input if these transients are less than 5 μs in duration.
  4.3.5 Minimum Load
  The TPS717xx is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS717xx employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.
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  4.4.3 Disabled
  The device is disabled under the following conditions:
  The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
  The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold.
  The device junction temperature is greater than the thermal shutdown temperature.
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