基于LM5021的电流模式 AC-DC PWM 升压控制器 - 系统集成论坛

LM5021 离线式脉宽调制 (PWM) 控制器包含有实现采用电流模式控制的高效离线式单端反激/正激电源转换器所需的所有特性。 LM5021 包含超低 (25μA) 启动电流特性，可最大程度降低高压启动网络中的功耗。跳周期模式可降低轻负载条件下的功耗，从而实现节能应用(ENERGY STAR®、CECP 等)。附加特性包括欠压锁定、逐周期电流限制、断续模式过载保护、斜率补偿、软启动和振荡器同步功能。这款高性能 8 引脚 IC 的总传播延迟不到 100ns，并且能够通过单个电阻设定 1MHz 的振荡器。

　　The LM5021 is a single ended current mode controller primarily intended for use in offline forward or flyback converters. It is also useful for boost converters. Low startup current and a wide UVLO hysteresis make low dissipation startup circuits simple to implement. An on board 7-V regulator supplies stable power for device operation and can supply external circuitry. A soft start function minimizes stresses during startup and allows the converter to come to steady state operating conditions gradually.

　　The device comes in two versions with different maximum duty cycles. The LM5021-1 has a maximum duty cycle of 80% while the LM5021-2 has a maximum duty cycle of 50%. For current mode control applications where the duty cycle can exceed 50%, slope compensation is implemented by simply adding a resistor between the LM5021-1 CS pin and the current sense filter capacitor.

　　Cycle-by-cycle overcurrent sensing provides robust protection. A 500-mV maximum current sense threshold minimizes power dissipation in supplies that sense the main switch current directly with a resistor. For a sustained overcurrent condition, the controller will enter a hiccup mode to reduce component stresses. The controller automatically restarts when the overload condition is removed.

　　The switching frequency is programmable using a single resistor connected from the RT pin to GND. For applications that require it, the switching frequency can be synchronized to an external clock source by capacitively coupling a pulse train into the RT pin.

　　Skip cycle operation is implemented to reduce input power and increase efficiency at light load conditions. For applications where this is not desirable, skip cycle operation may be disabled by adding an offset voltage to the CS pin.

　　The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The COMP pin voltage is reduced by 1.25 V then attenuated by a 3:1 resistor divider. The PWM comparator input offset voltage is designed such that less than 1.25 V at the COMP pin will result in a zero duty cycle at the controller output.

　　For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this oscillation can be avoided. The LM5021-1 integrates this slope compensation by summing a ramp signal generated by the oscillator with the current sense signal. The slope compensation is generated by a current ramp driven through an internal 1.8 kΩ resistor connected to the CS pin. Additional slope compensation may be added by increasing the resistance between the current sense filter capacitor and the CS pin, thereby increasing the voltage ramp created by the oscillator current ramp. Since the LM5021-2 is not capable of duty cycles greater than 50%, there is no slope compensation feature in this device.

　　The LM5021 provides a cycle-by-cycle over current protection feature. Current limit is triggered by an internal current sense comparator threshold which is set at 500 mV. If the CS pin voltage plus the slope compensation voltage exceeds 500 mV, the OUT pin output pulse will be immediately terminated.

　　An RC filter, located near the LM5021, is recommended for the CS pin to attenuate the noise coupled from the power FET's gate to source. The CS pin capacitance is discharged at the end of each PWM clock cycle by an internal switch. The discharge switch remains on for an additional 90ns leading edge blanking interval to attenuate the current sense transient that occurs when the external power FET is turned on. In addition to providing leading edge blanking, this circuit also improves dynamic performance by discharging the current sense filter capacitor at the conclusion of every cycle.

　　The LM5021 CS comparator is very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor, which should also be located close to the IC. If a current sense resistor located in the power FET's source is used for current sense, a low inductance resistor is required. In this case, all of the noise sensitive low current grounds should be connected in common near the IC and then a single connection should be made to the power ground (sense resistor ground point).

　　A single external resistor connected between RT and GND pins sets the LM5021 oscillator frequency. The LM5021-2 device, with 50% maximum duty cycle, includes an internal flip-flop that divides the oscillator frequency by two. This method produces a precise 50% maximum duty cycle limit. Because of this frequency divider, the oscillator frequency of the LM5021-2 is actually twice the frequency of the gate drive output (OUT). For the LM5021-1 device, the oscillator frequency and the operational output frequency are the same.